1. Field of the Invention
The present disclosure relates to multi-bank random access memory (RAM) structures and, more specifically, to embodiments of a multi-bank random access memory (RAM) structure (e.g., a multi-bank embedded dynamic random access memory (eDRAM) structure or a multi-bank static random access memory (SRAM) structure) with a combination of global and local signal buffering (e.g., global and local control, address, and data signal buffering) for improved performance.
2. Description of the Related Art
In multi-bank random access memory (RAM) structures, such as multi-bank embedded dynamic random access memory (eDRAM) structures and multi-bank static random access memory (SRAM) structures, the performance of the global connectors, which carry signals (e.g., control signals, address signals and data signals) from a memory controller to the local connectors for the various memory banks, is critical to overall memory performance (i.e., to memory timing parameters, such as slew and propagation delay). Unfortunately, as scaling continues through and beyond the 32 nm technology node, the resistance-capacitance (RC) time constant of the lines (i.e., wires) which form such global connectors has increased. This increase in the RC time constant negatively impacts the ability of the global connectors, which are relatively long, to adequately drive the signals from the memory controller to the memory banks (i.e., to drive the signal to the multiple circuit loads) and, thereby results in poor slew rates. Thus, designers have incorporated buffers into such global connectors (e.g., between every 8 memory banks, between every 4 memory banks, etc.). The added buffers improve the slew rates, but do so at the expense of increased area consumption, increased peak power consumption and increased latency. Therefore, there is a need in the art for a multi-bank RAM structure (e.g., a multi-bank eDRAM structure or a multi-bank SRAM structure) with more efficient signal buffering.